H27U4G8F2D Datasheet, PDF (19/62 Pages) Hynix Semiconductor – 4 Gbit (512M x 8 bit) NAND Flash

APCPCWM_4828539:WP_0000001WP_0000001
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H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
3.11 Read Status Register.
The device contains a Status Register to retrieve the status value for the last operation issued. After writing 70h command
to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of
CE# or RE#, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple
memory connections even when RB# pins are common-wired. Refer to Table 12 for specific Status Register definition,
and to Figure 10 and Figure 38 for timings.
If Read Status register command is issued during multi-plane operations Read Status Register polling shall return the
combined status value related to the outcome of the operation in the two planes according to this table:
Status Register bit
Bit 0, Pass/Fail
Bit 1, Cache Pass/Fail
Composite status value
OR
OR
Status register is dynamic in other words, user is not required to toggle RE# / CE# to update it.
The command register remains in Status Read mode until further commands are issued. Therefore, if the status register
is read during a random read cycle, the read command (00h) should be given before starting read cycles.
Note:
Read Status Register command shall not be used for concurrent operations in of multi-dice stack configurations (single
CE#). For this case, either "Read Status Enhanced" (Section 3.12) shall be used instead.
3.12 Read Status Enhanced
Read Status Enhanced is an additional feature used to retrieve the status value for a previous operation in the following
cases:
- on a specific die of a multi-dice stack configurations (single CE#), in case of concurrent operations
When 4Gbit dice are stacked(*) to form 8Gbit DDP or 16Gbit QDP (single CE#), it is possible to run a first operation on
the first 4Gbit, then activate a concurrent operation on the second (or third or fourth) device. (examples: Erase while
Read, Read while Program, etc.)
- on a specific plane in case of multi-plane operations in the same die.
Figure 39 defines the Read Status Enhanced behavior and timings. The plane and die address must be specified in the
command sequence in order to retrieve the status of the die and the plane of interest.
Refer to Table 12 for specific Status Register definition. The command register remains in Status Read mode until further
commands are issued.
Status register is dynamic in other words, user is not required to toggle RE# / CE# to update it.
Rev 1.4 / OCT. 2010
*ba53f20d-240c*
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