 English |
|
|
|
|
|
|
|
| H27U4G8F2D Datasheet, PDF (45/62 Pages) Hynix Semiconductor – 4 Gbit (512M x 8 bit) NAND Flash | |||
| |||
| ◁ |
APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
CLE
WE
ALE
RE
IOx
00h C1A C2A R1A R2A R3A 35h
SR[6]
tR
00h C1B C2B R1B R2B R3B 35h
tR
Figure 23: Multiple plane copy back read (ONFI 1.0 protocol)
A
NOTES:
C1A-C2A
R1A-R3A
C1B-C2B
R1B-R3B
Column address for page A. C1A is the least significant byte.
Row address for page A. R1A is the least significant byte.
Column address for page B. C1B is the least significant byte.
Row address for page B. R1B is the least significant byte.
CLE
WE
ALE
RE
IOx
SR[6]
85h C1C C2C R1C R2C R3C 11h
tIPBSY
85h C1D C2D R1D R2D R3D 10h
tPROG
Figure 24: Multiple plane copy back program (ONFI 1.0 protocol)
NOTES:
C1C-C2C Column address for page C. C1A is the least significant byte.
R1C-R3C Row address for page C. R1A is the least significant byte.
D0C-DnC Data to program for page C.
C1D-C2D Column address for page D. C1B is the least significant byte.
R1D-R3D Row address for page D. R1B is the least significant byte.
D0D-DnD Data to program for page D.
Same restrictions on address of pages C and D, and allowed commands as Figure 21 apply
Rev 1.4 / OCT. 2010
A
45
*ba53f20d-240c*
B34416/177.179.157.84/2010-10-08 10:08
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese