H27U4G8F2D Datasheet, PDF (15/62 Pages) Hynix Semiconductor – 4 Gbit (512M x 8 bit) NAND Flash

APCPCWM_4828539:WP_0000001WP_0000001
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H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
ically executes the algorithms and controls timings necessary for program and verify, thereby freeing the system con-
troller for other tasks. Once the program process starts, the Read Status Register commands (70h or 78h) may be
issued to read the status register. The system controller can detect the completion of a program cycle by monitoring
the RB# output, or the Status bit (I/O 6) of the Status Register. Only the Read Status commands (70h or 78h) or Reset
command are valid during programming is in progress. When the Page Program is complete, the Write Status Bit (I/O
0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the com-
mand register. Figure 14 and Figure 15 detail the sequence.
The device is programmed basically by page, but it also allows multiple partial page programming of a word or consec-
utive bytes up to 2112 (x8) or 1056 (x16) in a single page program cycle.
The number of consecutive partial page programming operations (NOP) within the same page must not exceed the
number indicated in Table 27. In addition, pages must be sequentially programmed within a block.
Users which use "EDC check" in copy back must comply with some limitations related to data handling during one
page program sequence. Please refer to Section 3.10 for details.
3.4. Multiple plane program
Device supports multiple plane program: it is possible to program 2 pages in parallel, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into
the appropriate cell. The serial data loading period begins with inputting the Serial Data Input command (80h), followed
by the five cycle address inputs and serial data for the 1^st page. Address for this page must be in the 1^st plane
(A<18>=0). The device supports random data input exactly same as in the case of page program operation. The Dum-
my Page Program Confirm command (11h) stops 1^st page data input and devices becomes busy for a short time (t_DBSY).
Once it has become ready again, either the traditional "81h" or the ONFI 1.0 "80h" command must be issued, followed
by 2^nd page address (5 cycles) and its serial data input. Address for this page must be in the 2^nd plane (A<18>=1).
Program Confirm command (10h) makes parallel programming of both pages to start. Figure 20 and Figure 21 de-
scribe the sequences.
User can check operation status by monitoring RB# pin or reading status register commands (70h or 78h), as if it were
a normal page program: read status register command is also available during Dummy Busy time (t_DBSY).
In case of fail in any of 1^st and 2^nd page program, fail bit of status register will be set however, in order to know which
page failed, ONFI 1.0 "read status enhanced" command must be issued Refer to section 3.11 for further info.
The number of consecutive partial page programming operations (NOP) within the same page must not exceed
the number indicated in Table 27. In addition, it is recommended to program pages sequentially within a block.
3.5. Block Erase
The Block Erase operation is done on a block basis. Block address loading is accomplished in 3 cycles initiated by an
Erase Setup command (60h). Only addresses A18 to A29 are valid while A12 to A17 are ignored. The Erase Confirm
command (D0h) following the block address loading initiates the internal erasing process This two-step sequence of
setup followed by execution command ensures that memory contents are not accidentally erased due to external noise
conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and
erase-verify.
Once the erase process starts, the Read Status Register commands (70h or 78h) may be issued to read the status
register. The system controller can detect the completion of an erase by monitoring the RB# output, or the Status bit
(I/O 6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid while eras-
ing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 19 details the sequence.
Rev 1.4 / OCT. 2010
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