H27U4G8F2D Datasheet, PDF (46/62 Pages) Hynix Semiconductor – 4 Gbit (512M x 8 bit) NAND Flash

APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
Two-Plane Block Erase Operation
CLE
CE
tWC
tWC
WE
ALE
tWB
tBERS
tWHR
RE
I/Ox
60h Row Add1 Row Add2 Row Add3
60h Row Add1 Row Add2 Row Add3 D0h
Row Address
Row Address
R/B
Block Erase Setup Command1
Block Erase Setup Command2
Erase Confirm Command
Ex.) Address Restriction for Two-Plane Block Erase Operation
70h
I/O0
Busy
Read Status Command
I/O 1 = 0 Successful Erase
I/O 1 = 1 Error in plane
R/B
tBERS
I/O0~7 _60h
Address 60h Address D0h
70h
Row Add1,2,3
Row Add1,2,3
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘Low’
A19 ~ A28 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘High’
A19 ~ A28 : Valid
Figure 25: Multiple plane block erase (traditional protocol)
NOTE: the figure refers to x8 case. Please refer to Section 1.4 for address remapping rules for the x16 case
Rev 1.4 / OCT. 2010
*ba53f20d-240c*
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B34416/177.179.157.84/2010-10-08 10:08