MC68HC08LT8 Datasheet, PDF (99/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port B
9.3.2 Data Direction Register B (DDRB)
Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to
a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
NOTE
For devices packaged in a 44-pin package, PTB6–PTB7 are not connected.
DDRB6:7 should be set to a 1 to configure PTB6–PTB7 as outputs.
Address:
Read:
Write:
Reset:
$0005
Bit 7
6
5
0
DDRB7 DDRB6
4
3
2
1
0
DDRB3 DDRB2 DDRB1
0
0
0
0
0
0
0
Figure 9-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB[7:6, 3:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:6, 3:0], configuring all port B
pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 9-7 shows the port
B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBX
PTBX
PTBX
READ PTB ($0001)
Figure 9-7. Port B I/O Circuit
When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 9-3 summarizes the operation of the port B pins.
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
99