MC68HC08LT8 Datasheet, PDF (79/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
8.4.2 LCD Voltages (V_LCD, V_LCD1, V_LCD2, V_LCD3)
The voltage V_LCD is from the V_LCD pin and must not exceed V_DD. V_LCD1, V_LCD2, and V_LCD3 are internal
bias voltages for the LCD driver waveforms. They are derived from V_LCD using a resistor ladder (see
Figure 8-3).
The relative potential of the LCD voltages are:
• V_LCD = V_DD
• V_LCD1 = 2/3 × (V_LCD – V_bias)
• V_LCD2 = 1/3 × (V_LCD – V_bias)
• V_LCD3 = V_bias
The V_LCD3 bias voltage, V_bias, is controlled by the LCD contrast control bits, LCCON[2:0].
8.4.3 LCD Cycle Frame
The LCD driver module uses the 32KXCLK (see Chapter 5 Oscillator (OSC)) as the input reference clock.
This clock is divided to produce the LCD waveform base clock, LCDCLK, by configuring the LCLK[2:0]
bits in the LCD clock register. The LCDCLK clocks the backplane and the frontplane output waveforms.
The LCD cycle frame is determined by the equation:
LCD CYCLE FRAME =
1
LCD WAVEFORM BASE CLOCK × DUTY
For example, for 1/3 duty and 256Hz waveform base clock:
1
LCD CYCLE FRAME =
256 × (1/3)
= 11.72 ms
8.4.4 Fast Charge and Low Current
The default value for each of the bias resistors (see Figure 8-3), R_LCD, in the resistor ladder is
approximately 37kΩ at V_LCD = 3V. The relatively high current drain through the 37kΩ resistor ladder may
not be suitable for some LCD panel connections. Lowering this current is possible by setting the LC bit in
the LCD control register, switching the R_LCD value to 146kΩ.
Although the lower current drain is desirable, but in some LCD panel connections, the higher current is
required to drive the capacitive load of the LCD panel. In most cases, the higher current is only required
when the LCD waveforms change state (the rising and falling edges in the LCD output waveforms). The
fast charge option is designed to have the high current for the switching and the low current for the steady
state. Setting the FC bit in the LCD control register selects the fast charge option. The R_LCD value is set
to 37kΩ (for high current) for a fraction of time for each LCD waveform switching edge, and then back to
146kΩ for the steady state period. The duration of the fast charge time is set by configuring the
FCCTL[1:0] bits in the LCD clock register, and can be LCDCLK/32, LCDCLK/64, or LCDCLK/128. Figure
8-4 shows the fast charge clock relative to the BP0 waveform.
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
79