MC68HC08LT8 Datasheet, PDF (103/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port D
9.5.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
6
5
4
3
2
1
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
0
0
0
Figure 9-13. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 9-14 shows the
port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 9-14. Port D I/O Circuit
When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 9-5 summarizes the operation of the port D pins.
Table 9-5. Port D Pin Functions
DDRD
Bit
PTD Bit
I/O Pin Mode
Accesses to DDRD
Read/Write
0
X⁽¹⁾
Input, Hi-Z⁽²⁾
DDRD[7:0]
1
X
Output
DDRD[7:0]
1. X = don’t care; except.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
Accesses to PTD
Read
Write
Pin
PTD[7:0]⁽³⁾
PTD[7:0]
PTD[7:0]
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
103