MC68HC08LT8 Datasheet, PDF(148/156 Page) Freescale Semiconductor, Inc

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MC68HC08LT8 Datasheet, PDF (148/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Electrical Specifications

16.8 5-V Control Timing

Table 16-7. Control Timing (5V)

Characteristic(1)

Symbol

Min

Max

Unit

Internal operating frequency

RST input pulse width low(2)

fOP

tIRL

100

MHz

IRQ interrupt pulse width low (edge-triggered)(3)

IRQ interrupt pulse period(3)

tILIH

100

tILIL

Note(4)

tCYC

1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise

noted.

2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.

3. Values are based on characterization results, not tested in production.

4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.

16.9 3-V Control Timing

Table 16-8. Control Timing (3V)

Characteristic(1)

Symbol

Min

Max

Unit

Internal operating frequency

RST input pulse width low(2)

fOP

tIRL

250

MHz

IRQ interrupt pulse width low (edge-triggered)(3)

IRQ interrupt pulse period(3)

tILIH

250

tILIL

Note(4)

tCYC

1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise

noted.

2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.

3. Values are based on characterization results, not tested in production.

4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.

16.10 2-V Control Timing

Table 16-9. Control Timing (2V)

Characteristic(1)

Symbol

Min

Max

Unit

Internal operating frequency

RST input pulse width low(2)

fOP

tIRL

500

MHz

IRQ interrupt pulse width low (edge-triggered)(3)

IRQ interrupt pulse period(3)

tILIH

500

tILIL

Note(4)

tCYC

1. VDD = 1.8 to 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise

noted.

2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.

3. Values are based on characterization results, not tested in production.

4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.

MC68HC08LT8 Data Sheet, Rev. 1

148

Freescale Semiconductor

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