MC68HC08LT8 Datasheet, PDF (80/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

Liquid Crystal Display (LCD) Driver
LCDCLK
LCD WAVEFORM
EXAMPLE: BP0
FAST CHARGE CLOCK
HIGH CURRENT SELECTED BEFORE SWITCHING EDGE,
PERIOD IS DEFINED BY FCCTL[1:0]
Figure 8-4. Fast Charge Timing
8.4.5 Contrast Control
The contrast of the connected LCD panel can be adjusted by configuring the LCCON[3:0] bits in the LCD
control register. The LCCON[3:0] bits provide a 16-step contrast control, which adjusts the bias voltage
in the resistor ladder for LCD voltage, V_LCD3. The relative voltages, V_LCD1 and V_LCD2, are altered
accordingly. For example, setting LCCON[3:0] = $F, the relative panel potential voltage (V_LCD – V_LCD3)
is reduced from maximum 3.3V to approximate 2.45V.
8.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The LCD driver module continues normal operation in wait mode. If the LCD is not required in wait mode,
power down the LCD module by clearing the LCDE bit before executing the WAIT instruction.
8.5.2 Stop Mode
For continuous LCD module operation in stop mode, the oscillator stop mode enable bit (STOP_XTALEN
in CONFIG2 register) must be set before executing the STOP instruction. When STOP_XTALEN is set,
32KXCLK continues to drive the LCD module.
If STOP_XTALEN bit is cleared, the LCD module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect LCD register states. LCD module operation resumes after an
external interrupt. To further reduce power consumption, the LCD module should be powered-down by
clearing the LCDE bit before executing the STOP instruction.
MC68HC08LT8 Data Sheet, Rev. 1
80
Freescale Semiconductor