MC68HC08LT8 Datasheet, PDF (91/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
LCLK2
0
0
0
0
1
1
1
1
LCLK1
0
0
1
1
0
0
1
1
Table 8-6. LCD Waveform Base Clock Selection
LCLK0
0
1
0
1
0
1
0
1
Divide
Ratio
128
256
512
1024
LCD Waveform Base Clock
Frequency LCDCLK (Hz)
f_XTAL = 32.768kHz
256
128
64
32
Reserved
Reserved
Reserved
Reserved
LCD Frame Rate
f_XTAL = 32.768kHz
1/3 duty
1/4 duty
85.3
64
42.7
32
21.3
16
10.7
8
8.8.3 LCD Data Registers (LDAT1–LDAT17)
The thirteen (13) LCD data registers enable and disable the drive to the corresponding LCD segments.
Addr.
$0052
$0053
$0054
$0055
$0056
$0057
$0058
Register Name
Bit 7
6
Read:
LCD Data Register 1
(LDAT1)
Write:
F1B3
F1B2
Reset: U
U
Read:
LCD Data Register 2
(LDAT2)
Write:
F3B3
F3B2
Reset: U
U
Read:
LCD Data Register 3
(LDAT3)
Write:
F5B3
F5B2
Reset: U
U
Read:
LCD Data Register 4
(LDAT4)
Write:
F7B3
F7B2
Reset: U
U
Read:
LCD Data Register 5
(LDAT5)
Write:
F9B3
F9B2
Reset: U
U
Read:
LCD Data Register 6
(LDAT6)
Write:
Reset:
F11B3
U
F11B2
U
Read:
LCD Data Register 7
(LDAT7)
Write:
Reset:
F13B3
U
F13B2
U
U = Unaffected
5
F1B1
U
F3B1
U
F5B1
U
F7B1
U
F9B1
U
F11B1
U
F13B1
U
4
3
F1B0
F0B3
U
U
F3B0
F2B3
U
U
F5B0
F4B3
U
U
F7B0
F6B3
U
U
F9B0
F8B3
U
U
F11B0 F10B3
U
U
F13B0 F12B3
U
U
= Unimplemented
2
F0B2
U
F2B2
U
F4B2
U
F6B2
U
F8B2
U
F10B2
U
F12B2
U
Figure 8-18. LCD Data Registers 1–13 (LDAT1–LDAT13)
1
F0B1
U
F2B1
U
F4B1
U
F6B1
U
F8B1
U
F10B1
U
F12B1
U
Bit 0
F0B0
U
F2B0
U
F4B0
U
F6B0
U
F8B0
U
F10B0
U
F12B0
U
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
91