MC68HC08LT8 Datasheet, PDF (36/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSC)
COP CLOCK
CGMXCLK (FROM OSC)
CGMXCLK (FROM OSC)
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 4-1. SIM Block Diagram
Addr.
Register Name
Bit 7
6
Read:
$FE00
Break Status Register
(BSR)
Write:
R
R
Reset: 0
0
Note: Writing a 0 clears SBSW.
Read: POR
PIN
$FE01
Reset Status Register
(RSR)
Write:
POR: 1
0
$FE02
Reserved
R
R
$FE03
Read:
Break Flag Control
Register (BFCR)
Write:
BCFE
R
Reset: 0
5
4
3
2
1
Bit 0
SBSW
R
R
R
R
R
NOTE
0
0
0
0
0
0
COP
ILOP
ILAD MODRST LVI
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
Figure 4-2. SIM I/O Register Summary
MC68HC08LT8 Data Sheet, Rev. 1
36
Freescale Semiconductor