MC68HC08LT8 Datasheet, PDF (48/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 4-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
IAB STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 4-18. Stop Mode Entry Timing
CGMXCLK
STOP RECOVERY PERIOD
INT/BREAK
IAB
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 4-19. Stop Mode Recovery from Interrupt or Break
4.7 SIM Registers
The SIM has three memory-mapped registers:
• SIM Break Status Register (SBSR)
• SIM Reset Status Register (SRSR)
• SIM Break Flag Control Register (SBFCR)
4.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop
mode or wait mode.
MC68HC08LT8 Data Sheet, Rev. 1
48
Freescale Semiconductor