MC68HC08LT8 Datasheet, PDF (90/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

Liquid Crystal Display (LCD) Driver
8.8.2 LCD Clock Register (LCDCLK)
The LCD clock register (LCDCLK):
• Selects the fast charge duty cycle
• Selects LCD driver duty cycle
• Selects LCD waveform base clock
Address:
Read:
Write:
Reset:
$004F
Bit 7
0
6
5
FCCTL1 FCCTL0
4
DUTY1
3
DUTY0
2
LCLK2
1
LCLK1
0
0
0
0
0
0
0
= Unimplemented
Figure 8-17. LCD Clock Register (LCDCLK)
Bit 0
LCLK0
0
FCCTL[1:0] — Fast Charge Duty Cycle Select
These read/write bits select the duty cycle of the fast charge duration. Reset clears these bits.
(See 8.4.4 Fast Charge and Low Current)
Table 8-4. Fast Charge Duty Cycle Selection
FCCTL1:FCCTL0
00
01
10
11
Fast Charge Duty Cycle
In each LCDCLK/2 period, each bias resistor is reduced to 37 kΩ
for a duration of LCDCLK/32.
In each LCDCLK/2 period, each bias resistor is reduced to 37 kΩ
for a duration of LCDCLK/64.
In each LCDCLK/2 period, each bias resistor is reduced to 37 kΩ
for a duration of LCDCLK/128.
Not used
DUTY[1:0] — Duty Cycle Select
These read/write bits select the duty cycle of the LCD driver output waveforms. The multiplexed
FP0/BP3 pin is controlled by the duty cycle selected. Reset clears these bits.
Table 8-5. LCD Duty Cycle Selection
DUTY1:DUTY0
00
01
10
11
Description
Static selected; FP0/BP3 pin function as FP0.
1/3 duty cycle selected; FP0/BP3 pin functions as FP0.
1/4 duty cycle selected; FP0/BP3 pin functions as BP3.
Not used
LCLK[2:0] — LCD Waveform Base Clock Select
These read/write bits selects the LCD waveform base clock. Reset clears these bits.
MC68HC08LT8 Data Sheet, Rev. 1
90
Freescale Semiconductor