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MC68HC08LT8 Datasheet, PDF (23/156 Pages) Freescale Semiconductor, Inc – Microcontrollers
Monitor ROM
Addr.
Register Name
Bit 7
6
Read: TOF
Timer 1 Status and Control
TOIE
$0020
Register Write: 0
(T1SC) Reset:
0
0
$0021
Timer 1 Counter Read: Bit 15
14
Register High Write:
(T1CNTH) Reset:
0
0
$0022
Timer 1 Counter Read: Bit 7
6
Register Low Write:
(T1CNTL) Reset:
0
0
Read:
Timer 1 Counter Modulo
Bit 15
14
$0023
Register High Write:
(T1MODH)
Reset: 1
1
Timer 1 Counter Modulo Read: Bit 7
6
$0024
Register Low Write:
(T1MODL) Reset:
1
1
Timer 1 Channel 0 Status and Read:
$0025
Control Register Write:
(T1SC0) Reset:
CH0F
0
0
CH0IE
0
$0026
Read:
Timer 1 Channel 0
Bit 15
14
Register High Write:
(T1CH0H) Reset:
$0027
Timer 1 Channel 0 Read: Bit 7
6
Register Low Write:
(T1CH0L) Reset:
Timer 1 Channel 1 Status and Read:
$0028
Control Register Write:
(T1SC1) Reset:
CH1F
0
0
CH1IE
0
$0029
Read:
Timer 1 Channel 1
Bit 15
14
Register High Write:
(T1CH1H)
Reset:
$002A
Timer 1 Channel 1 Read: Bit 7
6
Register Low Write:
(T1CH1L) Reset:
U = Unaffected
X = Indeterminate
5
4
3
0
0
TSTOP
TRST
1
0
0
13
12
11
2
1
Bit 0
PS2
PS1
PS0
0
0
0
10
9
Bit 8
0
0
0
0
0
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
13
12
11
10
9
Bit 8
1
1
1
1
1
1
5
4
3
2
1
Bit 0
1
1
1
1
1
1
MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
0
0
0
0
0
0
13
12
11
10
9
Bit 8
Indeterminate after reset
5
4
3
2
1
Bit 0
Indeterminate after reset
0
MS1A ELS1B ELS1A TOV1 CH1MAX
0
0
0
0
0
0
13
12
11
10
9
Bit 8
Indeterminate after reset
5
4
3
2
1
Bit 0
Indeterminate after reset
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
23