MC68HC08LT8 Datasheet, PDF (37/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Bus Clock Control and Generation
Addr.
$FE04
$FE05
$FE06
Register Name
Bit 7
Read: IF6
Interrupt Status Register 1
(INT1)
Write:
R
Reset: 0
Read: 0
Interrupt Status Register 2
(INT2)
Write:
R
Reset: 0
Read: 0
Interrupt Status Register 3
(INT3)
Write:
R
Reset: 0
6
5
IF5
IF4
R
R
0
0
0
0
R
R
0
0
0
0
R
R
0
0
= Unimplemented
4
3
2
1
Bit 0
IF3
IF2
IF1
0
0
R
R
R
R
R
0
0
0
0
0
0
IF10
IF9
IF8
IF7
R
R
R
R
R
0
0
0
0
0
0
0
0
IF16
0
R
R
R
R
R
0
0
0
0
0
R = Reserved
Figure 4-2. SIM I/O Register Summary (Continued)
4.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMXCLK as shown in Figure 4-3. This clock can
come from either the oscillator module or from the on-chip PLL. (See Chapter 5 Oscillator (OSC).)
OSCXCLK
÷2
CGMXCLK
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
OSC
SIM
Figure 4-3. SIM Clock Signals
4.2.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four.
4.2.2 Clock Start-up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
4.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. (See 4.6.2 Stop Mode.)
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
37