MC68HC08LT8 Datasheet, PDF (123/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

LVI Status Register
13.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF), the LVI will maintain a reset condition until
V_DD rises above the rising trip point voltage, V_TRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to V_TRIPF. V_TRIPR is greater than
V_TRIPF by the hysteresis voltage, V_HYS.
13.3.4 LVI Trip Selection
The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select whether the LVI is configured
for 5V or 3 V operation. (See Chapter 3 Configuration Register (CONFIG).)
NOTE
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V_TRIPF [5V] or V_TRIPF [3V]) may be lower than this. (See
Chapter 16 Electrical Specifications for the actual trip point voltages.)
13.4 LVI Status Register
The LVI status register (LVISR) controls LVI interrupt functions and indicates if the V_DD voltage was
detected below the V_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
LVIIF
0
0
0
0
0
LVIIE
Write:
LVIIACK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the V_TRIPF trip voltage
(see Table 13-1). Reset clears the LVIOUT bit.
Table 13-1. LVIOUT Bit Indication
V_DD
V_DD > V_TRIPR
V_DD < V_TRIPF
V_TRIPF < V_DD < V_TRIPR
LVIOUT
0
1
Previous value
LVIIE — LVI Interrupt Enable Bit
This read/write bit enables the LVIIF bit to generate CPU interrupt requests. Reset clears the LVIIE bit.
1 = LVIIF can generate CPU interrupt requests
0 = LVIIF cannot generate CPU interrupt requests
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
123