MC68HC08LT8 Datasheet, PDF (49/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Registers
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
Write:
R
R
R
R
R
Note⁽¹⁾
R
Reset:
0
R = Reserved
1. Writing a clears SBSW.
Figure 4-20. Break Status Register (BSR)
SBSW — Break Wait Bit
This status bit is set when a break interrupt causes an exit from wait mode or stop mode. Clear SBSW
by writing a logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break interrupt routine. The user can modify the return address on the stack
by subtracting 1 from it. The following code is an example.
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the break
service routine software.
HIBYTE EQU
LOBYTE EQU
If not SBSW, do RTI
BRCLR SBSW,SBSR, RETURN
;See if wait mode or stop mode was exited by
;break.
TST
LOBYTE,SP
;If RETURNLO is not zero,
BNE
DOLO
;then just decrement low byte.
DEC
HIBYTE,SP
;Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
;Point to WAIT/STOP opcode.
RETURN PULH
RTI
;Restore H register.
4.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits
have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit
and clears all other bits in the register
Address: $FE01
Bit 7
6
5
4
3
2
Read: POR
PIN
COP
ILOP
ILAD
0
Write:
POR: 1
0
0
0
0
0
= Unimplemented
1
Bit 0
LVI
0
0
0
Figure 4-21. Reset Status Register (RSR)
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
49