MC68HC08LT8 Datasheet, PDF (43/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

FROM RESET
Exception Control
I BBIRTESAEKT?
YES
INTERRUPT?
NO
YES
I-BIT SET?
NO
IRQ
INTERRUPT?
YES
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
STACK CPU REGISTERS
SET I-BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
YES
INSTRUCTION?
NO
RTI
YES
INSTRUCTION?
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 4-10. Interrupt Processing
4.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 4-11 demonstrates what happens when two interrupts are pending. If an interrupt is
pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
43