MC68HC08LT8 Datasheet, PDF (108/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long
as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See 4.5 Exception
Control.)
RESET
ACK
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
CLR
D
Q
CK
SYNCHRONIZER
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
IMASK
Addr.
$001E
MODE
HIGH
VOLTAGE
DETECT
Figure 10-1. IRQ Module Block Diagram
Register Name
Bit 7
IRQ Status and Control ^Read:
0
Register Write:
(INTSCR) _Reset:
0
6
5
0
0
0
0
= Unimplemented
4
3
0
IRQF
0
0
Figure 10-2. IRQ I/O Register Summary
TO MODE
SELECT
LOGIC
2
1
Bit 0
0
IMASK MODE
ACK
0
0
0
MC68HC08LT8 Data Sheet, Rev. 1
108
Freescale Semiconductor