MC68HC08LT8 Datasheet, PDF (42/156 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
• Reset
• Break interrupts
4.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 4-8 shows
interrupt entry timing, and Figure 4-9 shows interrupt recovery timing.
MODULE
INTERRUPT
I-BIT
IAB
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
IDB
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
R/W
MODULE
INTERRUPT
I-BIT
Figure 4-8. Interrupt Entry Timing
IAB
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
IDB
CCR
A
X PC – 1[15:8] PC – 1[7:0] OPCODE OPERAND
R/W
Figure 4-9. Interrupt Recovery Timing
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
(See Figure 4-10.)
MC68HC08LT8 Data Sheet, Rev. 1
42
Freescale Semiconductor