MC9S12XF512_1 Datasheet, PDF (952/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 20 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
When fault protection hardware disables PWM pins, the PWM generator continues to run, only the output
pins are deactivated.
The fault decoder disables PWM pins selected by the fault logic and the disable mapping register. See
Figure 20-15. Each bank of four bits in the disable mapping register control the mapping for a single PWM
pin. Refer to Table 20-11.
The fault protection is enabled even when the PWM is not enabled; therefore, a fault will be latched in and
will be cleared in order to prevent an interrupt when the PWM is enabled.
20.4.8.1 Fault Pin Sample Filter
Each fault pin has a sample filter to test for fault conditions. After every bus cycle setting the FAULTx pin
at logic zero, the filter synchronously samples the pin once every four bus cycles. QSMP determines the
number of consecutive samples that must be logic one for a fault to be detected. When a fault is detected,
the corresponding FAULTx pin flag, FFLAGx, is set. Clear FFLAGx by writing a logic one to it.
If the FIEx, FAULTx pin interrupt enable bit is set, the FFLAGx flag generates a CPU interrupt request.
The interrupt request latch remains set until:
• Software clears the FFLAGx flag by writing a logic one to it
• Software clears the FIEx bit by writing a logic zero to it
• A reset occurs
20.4.8.2 Automatic Fault Clearing
Setting a fault mode bit, FMODEx, configures faults from the FAULTx pin for automatic clearing.
When FMODEx is set, disabled PWM pins are enabled when the FAULTx pin returns to logic zero and a
new PWM half cycle begins. See Figure 20-76. Clearing the FFLAGx flag does not affect disabled PWM
pins when FMODEx is set.
FAULT PIN
PWMS ENABLED PWMS DISABLED ENABLED DISABLED
Figure 20-76. Automatic Fault Clearing
PWMS ENABLED
20.4.8.3 Manual Fault Clearing
Clearing a fault mode bit, FMODEx, configures faults from the FAULTx pin for manual clearing:
• PWM pins disabled by the FAULT0 pin or the FAULT2 pin are enabled by clearing the
corresponding FFLAGx flag. The time at which the PWM pins are enabled depends on the
corresponding QSMPx bit setting. If QSMPx = 00, the PWM pins are enabled on the next IP bus
cycle when the logic level detected by the filter at the fault pin is logic zero. If QSMPx = 01,10 or
MC9S12XF - Family Reference Manual, Rev.1.19
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