MC9S12XF512_1 Datasheet, PDF (586/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.6.9 Receive FIFO
This section provides a detailed description of the two receive FIFOs.
13.6.9.1 Overview
The receive FIFOs implement the queued receive buffer defined by the FlexRay Communications System
Protocol Specification, Version 2.1 Rev A. One receive FIFO is assigned to channel A, the other receive
FIFO is assigned to channel B. Both FIFOs work completely independent from each other.
The message buffer structure of each FIFO is described in Section 13.6.3.3, “Receive FIFO”. The area in
the FRM for each of the two receive FIFOs is characterized by:
• The index of the first FIFO entry given by Receive FIFO Start Index Register (RFSIR)
• The number of FIFO entries and the length of each FIFO entry as given by Receive FIFO Depth
and Size Register (RFDSR)
13.6.9.2 Receive FIFO Configuration
The receive FIFO control and configuration data are given in Section 13.6.3.7, “Receive FIFO Control and
Configuration Data”. The configuration of the receive FIFOs consists of two steps.
The first step is the allocation of the required amount of FRM for the FlexRay window. This includes the
allocation of the message buffer header area and the allocation of the message buffer data fields. For more
details see Section 13.6.4, “FlexRay Memory Layout”.
The second step is the programming of the configuration data register while the PE is in POC:config.
The following steps configure the layout of the FIFO.
• The number of the first message buffer header index that belongs to the FIFO is written into the
Receive FIFO Start Index Register (RFSIR).
• The depth of the FIFO is written into the FIFO_DEPTH field in the Receive FIFO Depth and Size
Register (RFDSR).
• The length of the message buffer data field for the FIFO is written into the ENTRY_SIZE field in
the Receive FIFO Depth and Size Register (RFDSR).
NOTE
To ensure, that the read index RDIDX always points to a message buffer that
contains valid data, the receive FIFO must have at least 2 entries.
The FIFO filters are configured through the fifo filter registers.
13.6.9.3 Receive FIFO Reception
The frame reception to the receive FIFO is enabled, if for a certain slots no message buffer is assigned or
subscribed. In this case the FIFO filter path shown in Figure 13-132 is activated.
When the receive FIFO filter path indicates that the received frame must be appended to the FIFO, the
FlexRay block writes the received frame header and slot status into the message buffer header field
MC9S12XF - Family Reference Manual, Rev.1.19
586
Freescale Semiconductor