MC9S12XF512_1 Datasheet, PDF (1155/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 26 Enhanced Capture Timer (ECT16B8CV3)
Table 26-29. Delay Counter Select Examples when PRNT = 1
DLY7
0
0
0
0
0
1
DLY6
0
0
0
0
1
1
DLY5
0
0
0
1
1
1
DLY4
0
0
1
1
1
1
DLY3
0
1
1
1
1
1
DLY2
1
1
1
1
1
1
DLY1
1
1
1
1
1
1
DLY0
1
1
1
1
1
1
Delay
32 bus clock cycles
64 bus clock cycles
128 bus clock cycles
256 bus clock cycles
512 bus clock cycles
1024 bus clock cycles
26.3.2.23 Input Control Overwrite Register (ICOVW)
Module Base + 0x002A
R
W
Reset
7
NOVW7
0
6
NOVW6
5
NOVW5
4
NOVW4
3
NOVW3
2
NOVW2
0
0
0
0
0
Figure 26-46. Input Control Overwrite Register (ICOVW)
Read: Anytime
Write: Anytime
All bits reset to zero.
1
NOVW1
0
0
NOVW0
0
Table 26-30. ICOVW Field Descriptions
Field
Description
7:0
NOVW[7:0]
No Input Capture Overwrite
0 The contents of the related capture register or holding register can be overwritten when a new input capture
or latch occurs.
1 The related capture register or holding register cannot be written by an event unless they are empty (see
Section 26.4.1.1, “IC Channels”). This will prevent the captured value being overwritten until it is read or
latched in the holding register.
26.3.2.24 Input Control System Control Register (ICSYS)
Module Base + 0x002B
R
W
Reset
7
SH37
0
6
SH26
5
SH15
4
SH04
3
TFMOD
2
PACMX
0
0
0
0
0
Figure 26-47. Input Control System Register (ICSYS)
Read: Anytime
Write: Once in normal modes
1
BUFEN
0
0
LATQ
0
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MC9S12XF - Family Reference Manual Rev.1.19
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