MC9S12XF512_1 Datasheet, PDF (925/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 20 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
Table 20-28. PMFENCB Field Descriptions (continued)
Field
Description
1
LDOKB
Load Okay B — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit loads the PRSCB bits, the PMFMODB register and the PWMVAL2-3 registers into a set of
buffers. The buffered prescaler divisor B, PWM counter modulus B value, PWM2–3 pulse widths take effect at
the next PWM reload.
Set LDOKB by reading it when it is logic zero and then writing a logic one to it. LDOKB is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKB.
0 Do not load new modulus B, prescaler B, and PWM2–3 values.
1 Load prescaler B, modulus B, and PWM2–3 values.
Note: Do not set PWMENB bit before setting the LDOKB bit and do not clear the LDOKB bit at the same time as
setting the PWMENB bit.
0
PWMRIEB
PWM Reload Interrupt Enable B — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit enables the PWMRFB flag to generate CPU interrupt requests.
0 PWMRFB CPU interrupt requests disabled
1 PWMRFB CPU interrupt requests enabled
20.3.2.26 PMF Frequency Control B Register (PMFFQCB)
Address: $0029
7
R
W
Reset
0
6
5
LDFQB
4
3
2
1
HALFB
PRSCB
0
0
0
0
0
0
Figure 20-32. PMF Frequency Control B Register (PMFFQCB)
Read anytime and write only if MTG is set.
0
PWMRFB
0
Table 20-29. PMFFQCB Field Descriptions
Field
7–4
LDFQB
3
HALFB
2–1
PRSCB
Description
Load Frequency B — This field selects the PWM load frequency according to Table 20-30. See
Section 20.4.7.2, “Load Frequency” for more details.
Note: The LDFQB field takes effect when the current load cycle is complete, regardless of the state of the load
okay bit, LDOKB. Reading the LDFQB field reads the buffered value and not necessarily the value
currently in effect.
Half Cycle Reload B — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
on edge-aligned PWMs.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
Prescaler B — This buffered field selects the PWM clock frequency illustrated in Table 20-31.
Note: Reading the PRSCB field reads the buffered value and not necessarily the value currently in effect. The
PRSCB field takes effect at the beginning of the next PWM cycle and only when the load okay bit, LDOKB,
is set.
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
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