MC9S12XF512_1 Datasheet, PDF (439/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 11 Memory Mapping Control (S12XMMCV4) SUPPORTING FLEXRAY
11.4.4.1 Master Bus Prioritization regarding access conflicts on Target Buses
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
• High priority¹ FLEXRAY access to XSRAM has priority over CPU, XGATE and BDM.
• CPU always has priority over BDM, FLEXRAY and XGATE.
• XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
for its duration.
• XGATE has priority over FLEXRAY and BDM.
• BDM has priority over CPU, FLEXRAY and XGATE when its access is stalled for more than 128
cycles. In the later case the suspect master will be stalled after finishing the current operation and
the BDM will gain access to the bus.
• In emulation modes all internal accesses are visible on the external bus as well and the external bus
is used during access to the PRU registers.
11.5 Initialization/Application Information
11.5.1 CALL and RTC Instructions
CALL and RTC instructions are uninterruptible CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
called can be located anywhere in the local address space or in any Flash or ROM page visible through the
program page window. The CALL instruction calculates and stacks a return address, stacks the current
PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value
controls which of the 256 possible pages is visible through the 16KB program page window in the 64KB
local CPU memory map. Execution then begins at the address of the called subroutine.
During the execution of the CALL instruction, the CPU performs the following steps:
1. Writes the current PPAGE value into an internal temporary register and writes the new instruction-
supplied PPAGE value into the PPAGE register
2. Calculates the address of the next instruction after the CALL instruction (the return address) and
pushes this 16-bit value onto the stack
3. Pushes the temporarily stored PPAGE value onto the stack
4. Calculates the effective address of the subroutine, refills the queue and begins execution at the new
address
This sequence is uninterruptible. There is no need to inhibit interrupts during the CALL instruction
execution. A CALL instruction can be performed from any address to any other address in the local CPU
memory space.
The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing
mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand
in the instruction. In indexed-indirect variations of the CALL instruction a pointer specifies memory
locations where the new page value and the address of the called subroutine are stored. Using indirect
1. FLEXRAY has two priority access types, one called high priority access and the other called normal access.
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
439