MC9S12XF512_1 Datasheet, PDF (464/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.2.1.5 TXD_B — Transmit Data Channel B
The TXD_B signal carries the transmit data for channel B to the corresponding FlexRay bus driver
13.2.1.6 TXE_B — Transmit Enable Channel B
The TXE_B signal indicates to the FlexRay bus driver that the FlexRay block is attempting to transmit data
on channel B.
13.2.1.7 STB3, STB2, STB1, STB0 — Strobe Signals
These signals provide the selected debug strobe signals. For details on the debug strobe signal selection
refer to Section 13.6.16, “Strobe Signal Support”.
13.3 Controller Host Interface Clocking
The clock for the CHI is derived from the system bus clock and has the same phase and frequency. Since
the FlexRay protocol requires data delivery at fixed points in time, the memory read cycles from the FRM
must be finished after a fixed amount of time. To ensure this, a minimum frequency f_chi of the CHI clock
is required, which is given in Equation 13-1.
f _chi ≥ 16MHz
Eqn. 13-1
Additional requirements for the minimum frequency of the CHI clock result from the number of message
buffer. The requirement is provides in Section 13.7.3, “Number of Usable Message Buffers”
13.4 Protocol Engine Clocking
The clock for the protocol engine can be generated by two sources. The first source is the internal crystal
oscillator and the second source is an internal PLL. The clock source to be used is selected by the clock
source select bit CLKSEL in the Module Configuration Register (MCR).
13.4.1 Oscillator Clocking
If the protocol engine is clocked by the internal crystal oscillator, an 80 MHz crystal or 80 MHz CMOS
compatible clock must be connected to the oscillator pins. The crystal or clock must fulfill the
requirements given by the FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
13.4.2 PLL Clocking
If the protocol engine is clocked by the dedicated internal PLL, which is described in Chapter 12, “Clock
Generation Module using IPLL (CGMIPLL) Block Description, the CGMIPLL must be programmed to
generate an output clock with f_CGMIPLL = 80 MHz.
MC9S12XF - Family Reference Manual, Rev.1.19
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