MC9S12XF512_1 Datasheet, PDF (26/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 1 MC9S12XF-Family Reference Manual
— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
— Transconductance sized for optimum start-up margin for typical crystals
• Clock and Reset Generator (CRG)
— Phase-locked-loop (IPLL) clock frequency multiplier
— Internally filtered. No external components required
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
— Fast wake up from STOP in self clock mode for power saving and immediate program
execution
• Non-Multiplexed External Bus (144 Pin package only)
— 16 data bits wide
— Support for external WAIT input or internal wait cycles to adapt MCU speed to peripheral
speed requirements
— Up to four chip select outputs to select 16K, 768K, 2M and 4MByte address spaces
— Supports glue less interface to popular asynchronous RAMs and Flash devices
— External address space 4MByte for Data and Program space
• FlexRay Module (FR)
— FlexRay protocol implementation according to FlexRay V2.1 Protocol Implementation
document
— Optimized programmers model to fit small address footprint
— Supports Data Rates of 2.5, 5, 8 and 10MBit/s
— The FlexRay clock can be derived from crystals ranging from 4MHz to 40MHz for cost and
EMC optimization
— FlexRay clocking independent from the CPU and XGATE bus frequency. Clock is generated
by a “dedicated” IPLL.
— Up to two channels for fault tolerant systems (see Table 1-2 Peripheral Feature Summary of
MC9S12XF-Family Members)
— Single channel operation on channel A, configurable to run FlexRay channel A or channel B
protocol
— 32 configurable message buffers
— Message buffers can be configured as Receive, single buffered Transmit or double buffered
Transmit message buffer
— Message buffer header, status and payload data stored in System RAM
— 2 independent message buffer segments
— Size of message buffer payload data section configurable from 0 up to 254 bytes
— 2 independent receive FIFOs, 1 per channel
— Six separate interrupt channels for Receive, receive FIFO channel A, receive FIFO channel B,
Transmit, Error and Wake-up
— Internal signals can be routed to I/O pins to ease debugging
• Analog-to-Digital Converter (ATD)
MC9S12XF - Family Reference Manual, Rev.1.19
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Freescale Semiconductor