MC9S12XF512_1 Datasheet, PDF (309/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 9 512 KByte Flash Module (S12XFTM512K3V1)
information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults, the priority for fault recording is:
1. Double bit fault over single bit fault
2. CPU over XGATE
Offset Module Base + 0x000E
7
6
5
4
3
2
1
0
R
ECCR[15:8]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
3
2
1
0
R
ECCR[7:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-21. Flash ECC Error Results Low Register (FECCRLO)
All FECCR bits are readable but not writable.
Table 9-27. FECCR Index Settings
ECCRIX[2:0]
FECCR Register Content
Bits [15:8]
Bit[7]
Bits[6:0]
000
Parity bits read from
Flash block
CPU or XGATE
source identity
Global address
[22:16]
001
Global address [15:0]
010
Data 0 [15:0]
011
Data 1 [15:0] (P-Flash only)
100
Data 2 [15:0] (P-Flash only)
101
Data 3 [15:0] (P-Flash only)
110
Not used, returns 0x0000 when read
111
Not used, returns 0x0000 when read
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
309