MC9S12XF512_1 Datasheet, PDF(482/1306 Page) Freescale Semiconductor, Inc – S12X Microcontrollers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC9S12XF512_1 Datasheet, PDF (482/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

◁

Chapter 13 FlexRay Communication Controller (FLEXRAY)

Field

9

RBIF

8

TBIF

7

MIE

6

PRIE

5

CHIE

4

WUPIE

3

FNEBIE

2

FNEAIE

1

RBIE

0

TBIE

Table 13-18. GIFER Field Descriptions (Sheet 2 of 2)

Description

Receive Message Buffer Interrupt Flag â This ï¬ag is set if for at least one of the individual receive message

buffers (MBCCSn.MTD = 0) both the interrupt ï¬ag MBIF and the interrupt enable bit MBIE in the corresponding

Message Buffer Conï¬guration, Control, Status Registers (MBCCSRn) are asserted. The application can not

clear this RBIF ï¬ag directly. This ï¬ag is cleared by the FlexRay block when all of the interrupt ï¬ags MBIF of the

individual receive message buffers are cleared by the application or if the application has cleared the interrupt

enables bit MBIE.

0 None of the individual receive message buffers has the MBIF and MBIE ï¬ag asserted.

1 At least one individual receive message buffer has the MBIF and MBIE ï¬ag asserted.

Transmit Buffer Interrupt Flag â This ï¬ag is set if for at least one of the individual single or double transmit

message buffers (MBCCSn.MTD = 0) both the interrupt ï¬ag MBIF and the interrupt enable bit MBIE in the

corresponding Message Buffer Conï¬guration, Control, Status Registers (MBCCSRn) are equal to 1. The

application can not clear this TBIF ï¬ag directly. This ï¬ag is cleared by the FlexRay block when either all of the

individual interrupt ï¬ags MBIF of the individual transmit message buffers are cleared by the application or the

host has cleared the interrupt enables bit MBIE.

0 None of the individual transmit message buffers has the MBIF and MBIE ï¬ag asserted.

1 At least one individual transmit message buffer has the MBIF and MBIE ï¬ag asserted.

Module Interrupt Enable â This ï¬ag controls if the module interrupt line is asserted when the MIF ï¬ag is set.

0 Disable interrupt line

1 Enable interrupt line

Protocol Interrupt Enable â This ï¬ag controls if the protocol interrupt line is asserted when the PRIF ï¬ag is set.

0 Disable interrupt line

1 Enable interrupt line

CHI Interrupt Enable â This ï¬ag controls if the CHI interrupt line is asserted when the CHIF ï¬ag is set.

0 Disable interrupt line

1 Enable interrupt line

Wakeup Interrupt Enable â This ï¬ag controls if the wakeup interrupt line is asserted when the WUPIF ï¬ag is

set.

0 Disable interrupt line

1 Enable interrupt line

Receive FIFO channel B Not Empty Interrupt Enable â This ï¬ag controls if the receive FIFO B interrupt line

is asserted when the FNEBIF ï¬ag is set.

0 Disable interrupt line

1 Enable interrupt line

Receive FIFO channel A Not Empty Interrupt Enable â This ï¬ag controls if the receive FIFO A interrupt line

is asserted when the FNEAIF ï¬ag is set.

0 Disable interrupt line

1 Enable interrupt line

Receive Buffer Interrupt Enable â This ï¬ag controls if the receive buffer interrupt line is asserted when the

RBIF ï¬ag is set.

0 Disable interrupt line

1 Enable interrupt line

Transmit Interrupt Enable â This ï¬ag controls if the transmit buffer interrupt line is asserted when the TBIF

ï¬ag is set.

0 Disable interrupt line

1 Enable interrupt line

MC9S12XF - Family Reference Manual, Rev.1.19

482

Freescale Semiconductor

▷