MC9S12XF512_1 Datasheet, PDF (788/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 16 S12X Debug (S12XDBGV3) Module
16.4.5.1.3 Storing with End-Trigger
Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point
the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the
address of a change of flow instruction the trigger event will not be stored in the Trace Buffer.
16.4.5.2 Trace Modes
The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in
the DBGTCR register. In each mode tracing of XGATE or CPU12X information is possible. The source
for the trace is selected using the TSOURCE bits in the DBGTCR register. The modes are described in the
following subsections. The trace buffer organization is shown in Table 16-42.
16.4.5.2.1 Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses will be stored.
COF addresses are defined as follows for the CPU12X:
• Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
• Destination address of indexed JMP, JSR, and CALL instruction.
• Destination address of RTI, RTS, and RTC instructions
• Vector address of interrupts, except for SWI and BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
COF addresses are defined as follows for the XGATE:
• Source address of taken conditional branches
• Destination address of indexed JAL instructions.
• First XGATE code address in a thread
Change-of-flow addresses stored include the full 23-bit address bus of CPU12X, the 16-bit address bus for
the XGATE module and an information byte, which contains a source/destination bit to indicate whether
the stored address was a source address or destination address.
NOTE
When an CPU12X COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets exectuted after the interrupt service routine.
MC9S12XF - Family Reference Manual, Rev.1.19
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