MC9S12XF512_1 Datasheet, PDF (913/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 20 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
Read anytime. This register cannot be modified after the WP bit is set.
Table 20-7. PMFFPIN Field Descriptions
Field
6, 4, 2, 0
FPINE[3:0]
Fault x Pin Enable
0 FAULTx pin is disabled for fault protection.
1 FAULTx pin is enabled for fault protection.
where x is 0, 1, 2 and 3
Description
20.3.2.7 PMF Fault Status Register (PMFFSTA)
Address: $0006
7
6
5
4
3
2
1
0
R
0
0
0
0
FFLAG3
FFLAG2
FFLAG1
FFLAG0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-10. PMF Fault Flag Register (PMFFSTA)
Read and write anytime.
Table 20-8. PMFFSTA Field Descriptions
Field
Description
6, 4, 2, 0
FFLAG[3:0]
Fault x pin Flag — This flag is set after the required number of samples have been detected after a rising edge
on the FAULTx pin. Writing a logic one to FFLAGx clears it. Writing a logic zero has no effect. The fault protection
is enabled when FPINEx is set even when the PWMs are not enabled; therefore, a fault will be latched in,
requiring to be cleared in order to prevent an interrupt.
0 No fault on the FAULTx pin.
1 Fault on the FAULTx pin.
Note: Clearing FFLAGx satisfies pending FFLAGx CPU interrupt requests.
where x is 0, 1, 2 and 3
20.3.2.8 PMF Fault Qualifying Samples Register (PMFQSMP)
Address: $0007
R
W
Reset
7
6
QSMP3
0
0
5
4
QSMP2
0
0
3
2
QSMP1
0
0
1
0
QSMP0
0
0
Figure 20-11. PMF Fault Qualifying Samples Register (PMFQSMP)
Read anytime. This register cannot be modified after the WP bit is set.
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
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