MC9S12XF512_1 Datasheet, PDF (1101/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

MODFEN
0
0
1
1
Chapter 25 Serial Peripheral Interface (S12SPIV5)
Table 25-2. SS Input / Output Selection
SSOE
0
1
0
1
Master Mode
SS not used by SPI
SS not used by SPI
SS input with MODF feature
SS is slave select output
Slave Mode
SS input
SS input
SS input
SS input
25.3.2.2 SPI Control Register 2 (SPICR2)
Module Base +0x0001
7
R
0
W
6
XFRW
5
4
3
2
0
0
MODFEN BIDIROE
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 25-4. SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 25-3. SPICR2 Field Descriptions
1
SPISWAI
0
0
SPC0
0
Field
Description
6
XFRW
4
MODFEN
3
BIDIROE
Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL
becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and
SPIDRL form a 16-bit data register. Please refer to Section 25.3.2.4, “SPI Status Register (SPISR) for
information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a
change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 8-bit Transfer Width (n = 8)⁽¹⁾
1 16-bit Transfer Width (n = 16)¹
Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration, refer to Table 25-2. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.
Freescale Semiconductor
MC9S12XF - Family Reference Manual, Rev.1.19
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