MC9S12XF512_1 Datasheet, PDF (80/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 1 MC9S12XF-Family Reference Manual
configured to use the CGMIPLL as its clock source (bit CLKSEL in register MCR, see section 13.5.2.4,
“Module Configuration Register (MCR)“ for more details).
It is the responsibility of the software to ensure that a stable 80MHz clock is supplied to the FlexRay
controller while it is enabled.
NOTE
FlexRay applications have to use the FlexRay IPLL as clock source for the
FlexRay protocol engine. The option to use the crystal as clock source is
only intended for test purposes.
The CGMIPLL has to be configured for 80MHz to guarantee FlexRay
functionality.
FlexRay needs a stable clock. Make sure the PLL is locked before enabling
FlexRay and make sure it remains locked while FlexRay is running.
Frequency modulation should be turned off on the FlexRay IPLL.
1.12.2 Entry into and exit from low power modes
To ensure correct entry into stop mode the software should perform the following steps:
1. Shut down the FlexRay Controller (see 13.7.2 Shut Down Sequence for more details)
2. Turn off the CGMIPLL module by clearing the PLLON bit in the CGMCTL register (see section
12.3.2.4 CGMIPLL Control Register (CGMCTL) for more details)
3. Perform additional application specific tasks and enter low power mode
Once the microcontroller is woken-up from the low power mode the firmware should perform the
following steps:
1. Turn on the CGMIPLL module by setting the PLLON bit in the CGMCTL register
2. Wait for the CGMIPLL to achieve lock by waiting for the LOCK bit in the CGMCTL register to
become set
3. Re-initialize the FlexRay controller (see 13.7.1 Initialization Sequence for more details)
MC9S12XF - Family Reference Manual, Rev.1.19
80
Freescale Semiconductor