MC9S12XF512_1 Datasheet, PDF (936/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 20 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
• Swap functionality
20.4.5 Deadtime Generators
While in the complementary mode, each PWM pair can be used to drive top/bottom transistors, as shown
in Figure 20-49. Ideally, the PWM pairs are an inversion of each other. When the top PWM channel is
active, the bottom PWM channel is inactive, and vice versa.
NOTE
To avoid a short-circuit on the DC bus and endangering the transistor, there
must be no overlap of conducting intervals between top and bottom
transistor. But the transistor’s characteristics make its switching-off time
longer than switching-on time. To avoid the conducting overlap of top and
bottom transistors, deadtime needs to be inserted in the switching period.
Deadtime generators automatically insert software-selectable activation delays into each pair of PWM
outputs. The deadtime register (PMFDTMx) specifies the number of PWM clock cycles to use for
deadtime delay. Every time the deadtime generator inputs changes state, deadtime is inserted. Deadtime
forces both PWM outputs in the pair to the inactive state.
A method of correcting this, adding to or subtracting from the PWM value used, is discussed next.
PWM
GENERATOR
CURRENT
STATUS
OUT0
MUX
OUT1
DEADTIME
GENERATOR
TOP (PWM0)
TOP/BOTTOM
TO FAULT
GENERATOR ^{BOTTOM (PWM1)} PROTECTION
PWM0 &
PWM1 _OUTCTL0
OUT2
MUX
OUT3
DEADTIME
GENERATOR
TOP (PWM2)
TOP/BOTTOM
TO FAULT
GENERATOR ^{BOTTOM (PWM3)} PROTECTION
PWM2 &
PWM3 _OUTCTL2
OUT4
MUX
OUT5
DEADTIME
GENERATOR
TOP (PWM4)
TOP/BOTTOM
TO FAULT
GENERATOR ^{BOTTOM (PWM5) PROTECTION}
PWM4 &
PWM5 _OUTCTL4
Figure 20-49. Deadtime Generators
MC9S12XF - Family Reference Manual, Rev.1.19
936
Freescale Semiconductor