MC9S12XF512_1 Datasheet, PDF (1018/1306 Pages) Freescale Semiconductor, Inc – S12X Microcontrollers

Chapter 22 Enhanced Programmable Interrupt Timer (S12XEPIT24B8CV1)
Table 22-2. PITFLT Field Descriptions
Field
Description
7:0
PITFLT[7:0]
PIT Force Load Bits for Timer 7-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PITFLT bit loads the
corresponding 16-bit timer load register into the 16-bit timer down-counter. Additionally, the corresponding PIT
Channel Stop Bit (PTCSTP register) is loaded. Force load also affects PIT channels which are configured to
externally triggered mode (see PITTRIGE register). Writing a zero has no effect. Reading this register returns
zero.
22.4.0.3 PIT Channel Enable Register (PITCE)
Module Base + 0x0002
R
W
Reset
7
PITCE7
0
Read: Anytime
Write: Anytime
6
PITCE6
5
PITCE5
4
PITCE4
3
PITCE3
2
PITCE2
0
0
0
0
0
Figure 22-5. PIT Channel Enable Register (PITCE)
Table 22-3. PITCE Field Descriptions
1
PITCE1
0
0
PITCE0
0
Field
Description
7:0
PITCE[7:0]
PIT Enable Bits for Timer Channel 7:0 — These bits enable the PIT channels 7-0. If PITCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PITCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-
counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
22.4.0.4 PIT Multiplex Register (PITMUX)
Module Base + 0x0003
R
W
Reset
7
PITMUX7
0
6
PITMUX6
5
PITMUX5
4
PITMUX4
3
PITMUX3
2
PITMUX2
0
0
0
0
0
Figure 22-6. PIT Multiplex Register (PITMUX)
Read: Anytime
Write: Anytime
1
PITMUX1
0
0
PITMUX0
0
1018
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor