MC908JL3ECPE Datasheet, PDF (93/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM
channel 0 status and control register. Setting MS0B disables the channel 1 status and control register
and reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation. See Table 8-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See
Table 8-3.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel
x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel
x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 8-3
shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
Table 8-3. Mode, Edge, and Level Selection
MSxB
X
X
0
0
0
0
0
0
1
1
1
MSxA
0
1
0
0
0
1
1
1
X
X
X
ELSxB
0
0
0
1
1
0
1
1
0
1
1
ELSxA
0
0
1
0
1
1
0
1
1
0
1
Mode
Configuration
Pin under Port Control; Initial Output Level High
Output Preset
Pin under Port Control; Initial Output Level Low
Capture on Rising Edge Only
Input Capture Capture on Falling Edge Only
Capture on Rising or Falling Edge
Output
Compare or
PWM
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Buffered Output
Compare or
Buffered
PWM
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
93