MC908JL3ECPE Datasheet, PDF (52/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
5.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–$FFFF ($FEFE–$FEFF in Monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 5.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the reset status register (RSR). (See 5.7 SIM Registers.)
5.3.1 External Pin Reset
The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum
of 67 2OSCOUT cycles, assuming that the POR was not the source of the reset. See Table 5-2 for details.
Figure 5-4 shows the relative timing.
Table 5-2. PIN Bit Set Timing
Reset Type
POR
All others
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
2OSCOUT
RST
IAB PC
VECT H VECT L
Figure 5-4. External Reset Timing
5.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 2OSCOUT cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(Figure 5-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR.
(See Figure 5-6.) Note that for POR resets, the SIM cycles through 4096 2OSCOUT cycles during which
the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge
of RST shown in Figure 5-5.
MC68HC908JL3E Family Data Sheet, Rev. 4
52
Freescale Semiconductor