MC908JL3ECPE Datasheet, PDF (89/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Signals
8.8 I/O Signals
Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1.
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin.
8.9 I/O Registers
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
8.9.1 TIM Status and Control Register (TSC)
The TIM status and control register does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: $0020
Bit 7
6
5
4
3
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
Reset: 0
0
1
0
0
= Unimplemented
2
1
Bit 0
PS2
PS1
PS0
0
0
0
Figure 8-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a zero to TOF. If another TIM overflow occurs before the clearing sequence is
complete, then writing zero to TOF has no effect. Therefore, a TOF interrupt request cannot be lost
due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
89