MC908JL3ECPE Datasheet, PDF (114/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to one. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. See 5.5 Exception
Control.
ACK
RESET
IRQPUD
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
D ^CLR Q
CK
IRQ
FF
SYNCHRO-
NIZER
IMASK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
Figure 11-1. IRQ Module Block Diagram
TO MODE
SELECT
LOGIC
Addr.
$001D
Register Name
Bit 7
Read: 0
IRQ Status and Control
Register (INTSCR)
Write:
Reset: 0
6
5
0
0
0
0
= Unimplemented
4
3
0
IRQF
0
0
Figure 11-2. IRQ I/O Register Summary
2
1
Bit 0
0
IMASK MODE
ACK
0
0
0
MC68HC908JL3E Family Data Sheet, Rev. 4
114
Freescale Semiconductor