MC908JL3ECPE Datasheet, PDF (102/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
9.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 9-4. ADC Data Register (ADR)
9.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
ADIV2 ADIV1 ADIV0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-5. ADC Input Clock Register (ADICLK)
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC
clock. Table 9-2 shows the available clock configurations. The ADC clock should be set to
approximately 1MHz.
Table 9-2. ADC Clock Divide Ratio
ADIV2
0
0
0
0
1
X = don’t care
ADIV1
0
0
1
1
X
ADIV0
0
1
0
1
X
ADC Clock Rate
ADC Input Clock ÷ 1
ADC Input Clock ÷ 2
ADC Input Clock ÷ 4
ADC Input Clock ÷ 8
ADC Input Clock ÷ 16
MC68HC908JL3E Family Data Sheet, Rev. 4
102
Freescale Semiconductor