MC908JL3ECPE Datasheet, PDF (74/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor ROM (MON)
Entering monitor mode with V_TST on IRQ, the COP is disabled as long as V_TST is applied to either the IRQ
or the RST. (See Chapter 5 System Integration Module (SIM) for more information on modes of
operation.)
If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF)
(Table 7-1 condition set 3, where applied voltage is V_DD), then all port B pin requirements and conditions,
including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements
when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the
state of IRQ or the RST.
Figure 7-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and
IRQ = V_DD. An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600.
POR RESET
IS VECTOR ^NO
BLANK?
YES
MONITOR MODE
NORMAL USER
MODE
EXECUTE
MONITOR
CODE
POR
NO
TRIGGERED?
YES
Figure 7-2. Low-Voltage Monitor Mode Entry Flowchart
Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising
edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU waits for the host to send eight security bytes. (See 7.4 Security.) After the
security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is
ready to receive a command. The break signal also provides a timing reference to allow the host to
determine the necessary baud rate.
In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors
are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware
instead of user code.
MC68HC908JL3E Family Data Sheet, Rev. 4
74
Freescale Semiconductor