MC908JL3ECPE Datasheet, PDF (112/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
Table 10-4. Port D Pin Functions
DDRD
Bit
0
1
PTD Bit
X⁽¹⁾
X
I/O Pin Mode
Input, Hi-Z⁽²⁾
Output
Accesses to
DDRD
Read/Write
DDRD[7:0]
DDRD[7:0]
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Accesses to PTD
Read
Pin
Pin
Write
PTD[7:0]⁽³⁾
PTD[7:0]
10.4.3 Port D Control Register (PDCR)
The port D control register enables/disables the pull-up resistor and slow-edge high current capability of
pins PTD6 and PTD7.
Address:
Read:
Write:
Reset:
$000A
Bit 7
6
5
4
3
2
1
0
0
0
0
SLOWD7 SLOWD6 PTDPU7
0
0
0
0
0
0
0
= Unimplemented
Figure 10-12. Port D Control Register (PDCR)
Bit 0
PTDPU6
0
SLOWDx — Slow Edge Enable
The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain, high current output (25mA sink)
of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull
PTDPUx — Pull-up Enable
The PTDPU6 and PTDPU7 bits enable the 5kΩ pull-up on PTD6 and PTD7 respectively, regardless
the status of DDRDx bit.
1 = Enable 5kΩ pull-up
0 = Disable 5kΩ pull-up
MC68HC908JL3E Family Data Sheet, Rev. 4
112
Freescale Semiconductor