MC908JL3ECPE Datasheet, PDF (62/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
IAB
$6E0B
32
Cycles
32
Cycles
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
2OSCOUT
Figure 5-17. Wait Recovery from Internal Reset
5.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in stop mode, stopping the CPU and
peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32.
This is ideal for applications using canned oscillators that do not require long start-up times from stop
mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register
(BSR).
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 5-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 5-18. Stop Mode Entry Timing
MC68HC908JL3E Family Data Sheet, Rev. 4
62
Freescale Semiconductor