MC908JL3ECPE Datasheet, PDF (125/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

COP Control Register
13.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1.
Address: $001F
Bit 7
6
Read:
COPRS
R
Write:
5
4
3
2
1
R
LVID
R
SSREC STOP
Reset: 0
0
0
0
0
0
0
R
= Reserved
Figure 13-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is 8176 × 2OSCOUT cycles
0 = COP timeout period is 262,128 × 2OSCOUT cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
13.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
Read:
5
4
3
2
Low byte of reset vector
1
Bit 0
Write:
Reset:
Clear COP counter
Unaffected by reset
Figure 13-3. COP Control Register (COPCTL)
13.5 Interrupts
The COP does not generate CPU interrupt requests.
13.6 Monitor Mode
The COP is disabled in monitor mode when V_TST is present on the IRQ pin or on the RST pin.
13.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
125