MC908JL3ECPE Datasheet, PDF (107/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port A
10.2.3 Port A Input Pull-up Enable Register (PTAPUE)
The port A input pull-up enable register (PTAPUE) contains a software configurable pull-up device for
each of the seven port A pins. Each bit is individually configurable and requires the corresponding data
direction register, DDRAx be configured as input. Each pull-up device is automatically and dynamically
disabled when its corresponding DDRAx bit is configured as output.
Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTA6EN
0
PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
0
0
0
0
0
Figure 10-5. Port A Input Pull-up Enable Register (PTAPUE)
PTA6EN — Enable PTA6 on OSC2
This read/write bit configures the OSC2 pin function when RC oscillator option is selected. This bit has
no effect for X-tal oscillator option.
1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and pull-up functions
0 = OSC2 pin outputs the RC oscillator clock (RCCLK)
PTAPUE[6:0] — Port A Input Pull-up Enable Bits
These read/write bits are software programmable to enable pull-up devices on port A pins
1 = Corresponding port A pin configured to have internal pull-up if its DDRA bit is set to 0
0 = Pull-up device is disconnected on the corresponding port A pin regardless of the state of its
DDRA bit
Table 10-2 summarizes the operation of the port A pins.
Table 10-2. Port A Pin Functions
PTAPUE Bit
DDRA
Bit
PTA Bit
1
0
X⁽¹⁾
0
0
X
I/O Pin Mode
Input, V_DD(2)
Input, Hi-Z⁽⁴⁾
Accesses to DDRA
Read/Write
DDRA[6:0]
DDRA[6:0]
X
1
X
Output
DDRA[6:0]
1. X = Don’t care.
2. I/O pin pulled to V_DD by internal pull-up.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High Impedance.
Accesses to PTA
Read
Pin
Pin
Write
PTA[6:0]⁽³⁾
PTA[6:0]⁽³⁾
PTA[6:0]
PTA[6:0]
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
107