 English |
|
|
|
|
|
|
|
| MC908JL3ECPE Datasheet, PDF (127/180 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
| |||
| ◁ |
Chapter 14
Low Voltage Inhibit (LVI)
14.1 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin
and generates a reset when the VDD voltage falls to the LVI trip (LVITRIP) voltage.
14.2 Features
Features of the LVI module include the following:
⢠Selectable LVI trip voltage
⢠Selectable LVI circuit disable
14.3 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module
contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to
monitor VDD voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determine at which VDD level the
LVI module should take actions.
The LVI module generates one output signal:
LVI Reset â an reset signal will be generated to reset the CPU when VDD drops to below the set trip
point.
VDD
LVID
LOW VDD
DETECTOR
VDD > LVITRIP = 0
VDD < LVITRIP = 1
LVI RESET
LVIT1
LVIT0
Figure 14-1. LVI Module Block Diagram
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
127
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese