MC908JL3ECPE Datasheet, PDF (72/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor ROM (MON)
RC CIRCUIT
FOR MC68HRC908JL3E/JK3E/JK1E
SW1 MUST BE AT POSITION B
V_DD
See Figure 16-1. RC vs. Frequency
(5V @25°C) for component values
vs. frequency.
OSC1
OSC2
0.1 μF
V_DD
EXT OSC
FOR MC68HC908JL3E/JK3E/JK1E
SW1 AT POSITION A OR B
FOR MC68HRC908JL3E/JK3E/JK1E
SW1 MUST BE AT POSITION A
V_DD
(50% DUTY)
0.1 μF
OSC1
OSC2
RST
H(R)C908JL3E
H(R)C908JK3E
H(R)C908JK1E
V_DD
V_SS
XTAL CIRCUIT
FOR MC68HC908JL3E/JK3E/JK1E
SW1 AT POSITION A OR B
9.8304 MHz
20 pF
MAX232
V_DD
1 _C1+
+
1 μF
3 _C1–
4 _C2+
+
1 μF
5 _C2–
DB9
2
7
3
8
V_CC ¹⁶
GND ¹⁵
2
V+
V– ⁶
10
9
+
1 μF
1 μF
+
V_TST
V_{DD 1 k}
8.5 V
1 μF
+
10 k
74HC125
6
5
74HC125
2
3
4
5
1
20 pF
A
SW1
(SEE NOTE 1)
B
V_DD
10 k
V_DD
10 k
V_DD
10 k
C
NOTES:
1. Monitor mode entry method:
(SEE NOTE 2)
D
SW1: Position A — High voltage entry (V_TST)
Clock source must be EXT OSC or XTAL CIRCUIT.
10 k
Bus clock depends on SW2.
SW1: Position B — Reset vector must be blank ($FFFE = $FFFF = $FF)
Bus clock = OSC1 ÷ 4.
2. Affects high voltage entry to monitor mode only (SW1 at position A):
SW2: Position C — Bus clock = OSC1 ÷ 4
SW2: Position D — Bus clock = OSC1 ÷ 2
5. See Table 16-4. DC Electrical Characteristics (5V) for V_TST voltage level requirements.
SW2
10 k
Figure 7-1. Monitor Mode Circuit
OSC1
OSC2
IRQ
PTB0
PTB1
PTB3
PTB2
MC68HC908JL3E Family Data Sheet, Rev. 4
72
Freescale Semiconductor