MC908JL3ECPE Datasheet, PDF (88/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
8.5 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE=1.
CHxF and CHxIE are in the TIM channel x status and control register.
8.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
8.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
8.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR).)
To allow software to clear status bits during a break interrupt, write a one to the BCFE bit. If a status bit
is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a zero to the BCFE bit. With BCFE at zero (its default
state), software can read and write I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at zero. After the break,
doing the second step clears the status bit.
MC68HC908JL3E Family Data Sheet, Rev. 4
88
Freescale Semiconductor