MC908JL3ECPE Datasheet, PDF (92/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM)
8.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)
Each of the TIM channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address:
Read:
Write:
Reset:
$0025
Bit 7
CH0F
0
0
TSC0
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Address:
Read:
Write:
Reset:
$0028
Bit 7
CH1F
0
0
TSC1
6
5
0
CH1IE
0
0
= Unimplemented
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Figure 8-7. TIM Channel Status and Control Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading the TIM channel x
status and control register with CHxF set and then writing a zero to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing zero to CHxF has no effect. Therefore,
an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MC68HC908JL3E Family Data Sheet, Rev. 4
92
Freescale Semiconductor