MC908JL3ECPE Datasheet, PDF (133/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Power Modes
15.4.4 Break Flag Control Register (BFCR)
The break control register contains a bit that enables software to clear status bits while the MCU is in a
break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset:
0
R = Reserved
Figure 15-7. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
15.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
15.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if SBSW is set (see 5.6 Low-Power Modes). Clear the SBSW bit by writing
zero to it.
15.5.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register.
See 5.7 SIM Registers.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
133